1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device capable of storing memory data corresponding to 1 bit of memory information represented as binary information, using two memory cells.
2. Description of the Background Art
In a DRAM (Dynamic Random Access Memory) as a representative example of semiconductor memory devices, generally, a memory cell storing 1 bit of data has one-transistor and one-capacitor structure. As the structure of the memory cell itself is simple, it has been used in various electronic equipment as most suitable for increasing degree of integration and capacity of semiconductor devices.
FIG. 13 is a circuit diagram showing a configuration of one of the memory cells arranged in a matrix of rows and columns in a memory cell array of a DRAM, in which each memory cell storing 1 bit of data has one-transistor and one-capacitor configuration (in the following, such a DRAM will be referred to as a single memory cell type DRAM).
Referring to FIG. 13, a memory cell 100 includes an N channel MOS transistor N101 and a capacitor C101. N channel MOS transistor N101 is connected to a bit line BL and capacitor C101, and has its gate connected to a word line WL. One end of capacitor C101 different from the end connected to N channel MOS transistor N101, is connected to a cell plate 110.
N channel MOS transistor N101 is driven by a word line WL which is activated only at the time of data writing and data reading, and it is turned ON only at the time of data writing and data reading and otherwise kept OFF.
Capacitor C101 stores binary information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d dependent on whether charges are stored or not. When data is written to capacitor C101, bit line BL is precharged in advance to a power supply voltage Vcc or the ground voltage GND, corresponding to the write data. When word line WL is activated, N channel MOS transistor N101 is turned on, and a voltage corresponding to the binary information xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is applied from bit line BL through N channel MOS transistor N101 to capacitor C101. Thus, capacitor C101 is charged/discharged, and data is written.
When data is to be read, bit line BL is precharged in advance to a voltage Vcc/2. When word line WL is activated, N channel MOS transistor N101 is turned on, and bit line BL and capacitor C101 are conducted. Consequently, a slight change in voltage corresponding to the state of charge of capacitor C101 appears on bit line BL, and the slight change in voltage is amplified by a sense amplifier, not shown, to the voltage Vcc or to the ground voltage GND. The voltage level of bit line BL corresponds to the state of the read data.
Here, in a memory cell of a DRAM, charges in capacitor C101 that represent the stored data leak because of various factors, and are lost gradually. Specifically, the memory data is lost as time passes. Therefore, in the DRAM, before it becomes impossible to detect the change in voltage of bit line BL corresponding to the stored data in data reading, a refresh operation is executed, that is, the data is read once and written again.
Though the refresh operation is indispensable in the DRAM, it is disadvantageous in view of obtaining higher speed of operation. As a solution to this problem, a technique has been known in which a twin memory cell type memory configuration is adapted to allocate two memory cells for one bit of memory data, so that interval between refresh operations can be made longer and speed of access to the memory data can be increased.
FIG. 14 is a circuit diagram representing a configuration of memory cells arranged in a matrix of rows and columns in the memory cell array of a twin memory cell type DRAM.
Referring to FIG. 14, the memory cell in the DRAM has the twin memory cell type configuration in which two memory cells 100A and 100B are allocated for 1 bit of memory data, for storing the memory data and the inverted data thereof, respectively. Memory cell 100A includes an N channel MOS transistor N102 and a capacitor C102, and memory cell 100B includes an N channel MOS transistor N103 and a capacitor C103.
N channel MOS transistor N102 is connected to one bit line BL of paired bit lines BL, /BL and to capacitor C102, and has its gate connected to word line WLn (n is an even number not smaller than 0). N channel MOS transistor N102 is driven by word line WLn that is activated only at the time of data writing and data reading, and the transistor is turned ON only at the time of data writing and data reading and otherwise kept OFF.
N channel MOS transistor 103 is connected to the other bit line /BL of the paired bit lines BL, /BL and to capacitor C103, and has its gate connected to word line WLn+1. N channel MOS transistor N103 is driven by word line WLn+1 activated simultaneously with word line WLn, and the transistor is turned ON only at the time of data writing and data reading, and otherwise kept OFF.
Capacitors C102 and C103 store binary information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, dependent on whether charges are stored or not. Capacitor C103 stores inverted data of the data stored in capacitor C102. Capacitor C102 has one end connected to N channel MOS transistor N102 and another end connected to a cell plate 110. Capacitor C103 has one end connected to N channel MOS transistor N103 and another end connected to cell plate 110.
When memory data of 1 bit is to be written to capacitors C102 and C103, bit line BL is precharged to one of the power supply voltage Vcc and the ground voltage GND in correspondence with the write data, and bit line /BL is precharged to the other voltage, different from that of bit line BL. As word lines WLn and WLn+1 are simultaneously activated, N channel MOS transistors N102 and N103 are simultaneously turned ON, a voltage corresponding to the memory data is applied from bit line BL through N channel MOS transistor N102 to capacitor C103, and a voltage corresponding to the inverted data of the memory data is applied from bit line /BL through N channel MOS transistor N103 to capacitor C103. Consequently, 1 bit of memory data is written to capacitors C102 and C103.
When the memory data is to be read, the pair of bit lines BL and /BL are both precharged in advance to the voltage Vcc/2. When word lines WLn and WLn+1 are simultaneously activated, N channel MOS transistors N102 and N103 are simultaneously turned ON, bit line BL is conducted to capacitor C102 and bit line /BL is conducted to capacitor C103 Thus, slight changes in voltages in opposite directions to each other appear on the pair of bit lines BL and /BL, and a sense amplifier, not shown, detects potential difference between the pair of bit lines BL and /BL and amplifies the difference to the voltage Vcc or to the ground voltage GND. The amplified voltage level corresponds to the state of the read memory data.
In the twin memory cell configuration, two memory cells are allocated to 1 bit of data. Therefore, the memory cell area is surely doubled as compared with the conventional memory cell. As the two memory cells store mutually inverted information, however, the amplitude of potential difference between the pair of bit lines BL and /BL is large, and therefore operation becomes stable and interval between refresh operations can advantageously be made longer.
Further, in the present twin memory cell type DRAM, the pair of bit lines BL and /BL are precharged to the voltage xc2xdVcc, as in a single memory cell type DRAM described above, at the time of data reading. Here, when the memory data is read to the pair of bit lines BL and /BL, the amplitude of voltage change on the bit lines corresponding to the memory data is double that of the single memory cell type DRAM described above, as the voltages on the pair of bit lines BL and /BL change in directions opposite to each other. Thus, the twin memory cell type DRAM additionally has an advantage that high speed access to the data is possible at the time of data reading.
As described above, the single memory cell type DRAM shown in FIG. 13 and the twin memory cell type DRAM shown in FIG. 14 both have the same basic structure of memory cells, with an only difference being whether one memory cell or two memory cells are to be allocated to 1 bit of memory data. Therefore, in the process of manufacturing semiconductor memory devices, it would be convenient if the single memory cell type and twin memory cell type devices are manufactured not separately from the start and the single memory cell type devices could be switched to twin memory cell type devices in the middle of the manufacturing process, since such switching enables reduction in the number of process steps, flexibility in accordance with orders and hence possibly reduces manufacturing cost.
When the single memory cell type device is to be switched to the twin memory cell type device, switching may be possible by changing a pattern of aluminum interconnection in the step of interconnection. When this method is used, however, a separate mask pattern must be used, which means that the step of masking is also different. Therefore, sufficient reduction of manufacturing cost cannot be attained.
If electrical switching rather than structural switching of the semiconductor memory device is possible, a uniform mask pattern can be used both for the single memory cell type and twin memory cell type devices and the step of masking can be the same. Therefore, manufacturing cost can significantly be reduced.
The present invention was made to solve the above described problems and its object is to provide a semiconductor memory device that allows switching of single memory cell type configuration of memory cell to twin memory cell type configuration, with the switching performed electrically.
According to the present invention, the semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines arranged in the row direction; a plurality of bit line pairs arranged in the column direction; and a decoder selecting a word line and a bit line pair corresponding to an address signal specifying each of the plurality of memory cells among the plurality of word lines and the plurality of bit line pairs, respectively, wherein the decoder selects, when a twin cell mode signal for storing memory data corresponding to 1 bit of memory information represented as binary information using two memory cells is activated, the word line and the bit line pair for activating two memory cells, and the two memory cells store memory data and inverted data of the memory data, respectively.
Preferably, the decoder generates an internal row address signal for selecting the word line corresponding to the address signal, and when the twin cell mode signal is activated, simultaneously selects a first word line corresponding to a prescribed bit of internal row address signal which is at a first logic level, and a second word line corresponding to the prescribed bit which is at a second logic level.
Preferably, the prescribed bit is the least significant bit of the internal row address signal, and the decoder allocates the most significant bit of the address signal which is not used when the twin cell mode signal is active to the least significant bit of the internal row address signal, and allocates the least significant bit of the address signal to the most significant bit of the internal row address signal.
Preferably, the semiconductor memory device further includes a refresh control circuit for periodically executing the refresh operation to retain stored information. The refresh control circuit generates a refresh row address for designating a memory cell row as an object of the refresh operation, and the refresh row address includes a partial self refresh address bit of at least 1 bit, for designating execution of the refresh operation on a part of the memory cell array. The decoder includes a selecting circuit for selecting a partial self refresh address bit of at least of 1 bit among the refresh row addresses which is differ according to whether the two cell mode signal is activated or not.
As described above, in the semiconductor memory device according to the present invention, based on a twin cell mode signal, the semiconductor memory device functioning as a common single memory cell type device is electrically switched to a semiconductor memory device functioning as a twin memory cell type device.
Therefore, by the semiconductor memory device of the present invention, it becomes unnecessary to switch and separately prepare mask patterns. Therefore, the number of masks can be reduced and the number of process steps can be reduced, enabling reduction in manufacturing cost.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.